The present invention relates to digital PLL pulse generating apparatus, and specifically relates to a digital PLL pulse generating apparatus, which make it possible to instantaneously generate digital PLL pulses in a stable mode.
Various kinds of digital circuits require clock signals to drive operations of the circuits. The clock signals have been generated in the apparatus by clock signal generating circuits employing various kinds of methods.
In the almost cases mentioned above, pulse width conditions or timing conditions required by the various kinds of digital circuits cannot be directly derived from the reference clock signals serving as a reference. In general practices, such the pulse width conditions or timing conditions have been obtained from the reference clock signals generated by the clock generating circuit by utilizing the delay time inherently included in the circuit or employing a specific delay element.
With respect to the clock signals, since a conditional range of the clock signals is optimally set depending on the device under operation, it becomes impossible to insure the normal operation of the device, when the conditional range of the clock signals deviates from the optimum range.
Associating with the recent trend of the high-speed processing in the apparatus, the operating velocities of the devices included in the apparatus also have increased, and therefore, the clock frequencies are apt to increase and the optimum ranges of the output pulses required for the devices are apt to become narrow.
The operating environment of the devices included in the apparatus, however, is inherently unstable, and sometimes, fluctuations of physical conditions, such as an output voltage of the power source, a peripheral temperature, humidity, environmental conditions of the elements and wiring in the circuit, etc., would influence the circuit operations. Accordingly, when such the factors influence the circuit, which generates the abovementioned output pulses or processing pulses, the output pulses would be possibly fluctuated.
To cope with the above problem, many kinds of devices, in which inputted clock signals are phase-locked by the PLL circuit (the Phase Locked Loop Circuit) embedded in the integrated circuit to utilize the stable clock signals in the device, have been proposed for this purpose.
However, in the commercialized integrated circuits, such as the ASIC (the Application Specific Integrated Circuit), etc., there have bee problems that a normal operation is not insured in respect to discontinuous clock signals, and/or a feedback loop operated in the IC requires a long setup time.
To overcome the abovementioned drawbacks in conventional PLL circuits, it is an object of the present invention to provide digital PLL pulse generating apparatus, which make it possible to stably provide pulses having a desired timing.
Accordingly, to overcome the cited shortcomings, the abovementioned object of the present invention can be attained by digital PLL pulse generating apparatus described as follow.
(1) An apparatus for generating a digital PLL pulse, comprising: a delay-chain section having a plurality of delay elements coupled in serial to form a plurality of delayed clock signals, delayed states of which are different relative to each other in respect to reference clock signals; a synchronized-signal detecting section to select a plurality of delayed clock signals out of the delayed clock signals formed by the delay-chain section, and to output synchronizing information being equivalent to a number of delay stages for one period based on the selected delayed clock signals; a pulse forming section to form an output pulse having a desired pulse width and a desired timing by selecting a desired delayed clock signal out of the delayed clock signals formed by the delay-chain section, based on the synchronizing information outputted by the synchronized-signal detecting section and pulse forming information for forming a desired pulse; a feedback section to receive a feedback pulse returned from an external device as a result of loading the output pulse onto the external device, and to detect a phase difference between the feedback pulse and the output pulse; and a correcting section to correct a timing of the output pulse formed by the pulse forming section in response to the phase difference detected by the feedback section.
(2) The apparatus of item 1, further comprising: a memory section to store the phase difference between the feedback pulse and the output pulse; wherein the correcting section corrects a timing of the output pulse so as to cancel the phase difference stored in the memory section.
(3) The apparatus of item 1, wherein a detecting operation for detecting the phase difference between the feedback pulse and the output pulse and a correcting operation for correcting the timing of the output pulse are performed in a time-sharing mode by a single device.
(4) The apparatus of item 1, wherein the apparatus comprises two combinations of the delay-chain section and the synchronized-signal detecting section, and in one of the two combinations, the phase difference between the feedback pulse and the output pulse is detected, while in another one of the two combinations, the timing of the output pulse is corrected based on the phase difference.
(5) An apparatus for generating a digital PLL pulse, comprising: a first delay-chain section having a plurality of delay elements coupled in serial to form a plurality of delayed clock signals, delayed states of which are different relative to each other in respect to reference clock signals; a second delay-chain section having a plurality of delay elements coupled in serial to form a plurality of delayed output pulses, delayed states of which are different relative to each other in respect to output pulses; a first synchronized-signal detecting section to select a plurality of delayed clock signals out of the delayed clock signals formed by the first delay-chain section, and to output first synchronizing information being equivalent to a number of delay stages for one period based on the selected delayed clock signals; a second synchronized-signal detecting section to select the output pulses or a plurality of delayed output pulses, which are synchronized with feedback pulses returned from an external device as a result of loading the output pulses onto the external device, out of the delayed output pulses formed by the second delay-chain section, and to output second synchronizing information being equivalent to a number of delay stages for one period based on the selected delayed output pulses; a pulse forming section to form the output pulses, each of which has a desired pulse width and a desired timing so as to cancel fluctuations of the feedback pulses in respect to the output pulses, by selecting a desired delayed clock signal out of the delayed clock signals formed by the first delay-chain section based on the first synchronizing information, the second synchronizing information and pulse forming information for forming a desired pulse.
(6) The apparatus of item 5, wherein the apparatus also performs an operation for forming the output pulses in parallel so as to cancel fluctuations of the feedback pulses in respect to output of the first synchronizing information, output of the second synchronizing information and the output pulses.
(7) The apparatus of item 5, wherein the second synchronizing information includes a relative state between the reference clock signals and the feedback pulses, and, a relative state between the output pulses and the feedback pulses.
(8) The apparatus of item 1, wherein each of the delay-chain section, the synchronized-signal detecting section, the pulse forming section, the feedback section and the correcting section is integrated into an integrated circuit.
(9) The apparatus of item 1, wherein each of the delay-chain section, the synchronized-signal detecting section, the pulse forming section, the feedback section and the correcting section is a digital circuit.
(10) The apparatus of item 1, further comprising: a CPU (Central Processing Unit) to control each of the delay-chain section, the synchronized-signal detecting section, the pulse forming section, the feedback section and the correcting section.
Further, to overcome the abovementioned problems, other digital PLL pulse generating apparatus, embodied in the present invention, will be described as follow:
(11) A digital PLL pulse generating apparatus, characterized in that, the digital PLL pulse generating apparatus comprises:
a delay-chain section, in which delay elements are coupled in chain-connection to form a plurality of delayed clock signals by delaying reference clock signals;
a synchronized-signal detecting section to select delayed clock signals synchronized with the reference clock signals from the delay-chain section, and to derive synchronizing information being equivalent to a number of delay stages for one period from information of the selected delayed clock signals;
pulse forming means for forming an output pulse having a desired pulse width and a desired timing by selecting desired delayed clock signals from the delay-chain section while referring to the synchronizing information derived by the synchronized-signal detecting section and pulse forming information for forming a desired pulse;
feedback means for detecting a phase difference by comparing the feedback pulse with the output pulse formed by the pulse forming means; and
correcting means for correcting a timing of the output pulse formed by the pulse forming means in response to the phase difference detected by the feedback means.
(12) The digital PLL pulse generating apparatus, cited in item 11, characterized in that, the correcting means comprises a memory section to store the phase difference between the feedback pulse and the output pulse and corrects a timing of the output pulse so as to cancel the phase difference stored in the memory section.
(13) The digital PLL pulse generating apparatus, cited in item 11 or item 12, characterized in that, a detecting operation for detecting the phase difference due to the feedback and a correcting operation for correcting the timing of the output pulse in response to the detected phase difference are performed in a time-sharing mode by the same device
(14) The digital PLL pulse generating apparatus, cited in item 11 or item 12, characterized in that, the digital PLL pulse generating apparatus comprises two systems of the delay-chain sections and synchronized-signal detecting sections, and performs a detecting operation for detecting the phase difference due to the feedback and a correcting operation for correcting the timing of the output pulse in response to the detected phase difference in parallel.
(15) A digital PLL pulse generating apparatus, characterized in that, the digital PLL pulse generating apparatus comprises:
a first delay-chain section, in which delay elements are coupled in chain-connection to form a plurality of delayed clock signals;
a second delay-chain section, in which delay elements are coupled in chain-connection to form a plurality of delayed clock signals or a plurality of delayed feedback pulses
a first synchronized-signal detecting section to select delayed clock signals synchronized with the reference clock signals from the first delay-chain section, and to derive first synchronizing information being equivalent to a number of delay stages for one period from information of the selected delayed clock signals;
a second synchronized-signal detecting section to select delayed clock signals synchronized with either the output pulses or feedback pulses from the second delay-chain section, and to derive second synchronizing information being equivalent to a number of delay stages for one period from information of the selected delayed clock signals; and
pulse forming means for forming an output pulse having a desired pulse width and a desired timing so as to cancel fluctuations of the feedback pulses, by selecting necessary delayed clock signals from the delay-chain section while referring to the first synchronizing information derived by the first synchronized-signal detecting section, the second synchronizing information derived by the second synchronized-signal detecting section and pulse forming information for forming a desired pulse.
(16) The digital PLL pulse generating apparatus, cited in item 15, characterized in that, the digital PLL pulse generating apparatus performs in parallel the deriving operation of the first synchronizing information, the deriving operation of the second synchronizing information and the forming operation of the output pulses to cancel fluctuations of the feedback pulses.
(17) The digital PLL pulse generating apparatus, cited in item 15 or item 16, characterized in that, the second synchronizing information derived by the second synchronized-signal detecting section includes a state between the reference clock signals and the feedback pulses, and, a state between the output pulses and the feedback pulses.
(18) The digital PLL pulse generating apparatus, cited in any one of items 11-17, characterized in that, each of the sections is structured by an integrated circuit.
(19) The digital PLL pulse generating apparatus, cited in any one of items 11-18, characterized in that, each of the sections is structured by a digital circuit.
(20) The digital PLL pulse generating apparatus, cited in any one of items 11-19, characterized in that, the pulse forming means is controlled by a CPU (Central Processing Unit).
According to the digital PLL pulse generating apparatus of the present invention, cited in items 11-20, by reselecting clock signals depending on the feedback result after generating the objective processing pulses by selecting from a plurality of clock signals, it becomes possible to improve a response time from starting the phase comparing operation to obtaining output pulses having a desired timing.
In other words, by performing the feedback operation in a digital processing mode, it becomes possible to stably provide pulses having a desired timing, irrespective of various kinds of variable factors.
Further, according to the digital PLL pulse generating apparatus of the present invention, cited in items 11-13, since a plurality of time-shared operations are performed by a single circuit system, it becomes possible to simplify the circuit configuration.
Still further, according to the digital PLL pulse generating apparatus of the present invention, cited in items 14-16, since two operations are performed in parallel by two circuit systems, it becomes possible to real-timely perform the compensating operation by applying the feedback.
Still further, since the digital PLL pulse generating apparatus, embodied in the present invention, works in the digital processing mode, it is suitable for being integrated into an integrated circuit, as described in item 18.
Still further, since the digital PLL pulse generating apparatus, embodied in the present invention, works in the digital processing mode, it is suitable for being structured by digital circuits, as described in item 19.
Still further, since the digital PLL pulse generating apparatus, embodied in the present invention, works in the digital processing mode, it is suitable for being structured to be controlled by a CPU, as described in item 20.